Exemplary embodiments of the present invention relate to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating a semiconductor device including a buried bit line coupled to a one side contact.
Typical metal-oxide-semiconductor field effect transistors (MOSFET) have limitations in improving the scale of integration due to leakage current, power-on current, and short channel effect caused by extreme micronization of devices. Therefore, a typical method has been suggested to use a vertical channel protruding from a substrate instead of a typical planar channel in order to overcome the limitations.
The structure and limitations of a typical vertical channel type semiconductor device are described in detail below in accordance with the drawings.
FIGS. 1A and 1B illustrate a structure of a typical vertical channel type semiconductor device. FIG. 1A illustrates a perspective view of the semiconductor device, and FIG. 1B illustrates a plan view of the semiconductor device.
Referring to FIGS. 1A and 1B, the typical vertical channel type semiconductor device includes a plurality of pillars 11 protruding from a substrate 10, a plurality of buried bit lines (BBL) extending parallel to each other along a first direction I-I′, and a plurality of word lines (WL) extending parallel to each other along a second direction II-II′ which intersects with the first direction I-I′.
In detail, the typical vertical channel type semiconductor device includes a plurality of pillar structures having the pillars 11 and hard mask layers 14 extending in a vertical direction. Each pillar 11 has a surrounding type gate electrode 13 forming the cylindrical surface, and a gate insulation layer 12 is formed on at an interface between each pillar 11 and its corresponding surrounding type gate electrode 13.
The buried bit lines are formed by implanting ions of impurities into the substrate 10. Trenches T are formed between adjacent buried bit lines. Although not shown, insulation layers are formed in the trenches T to isolate adjacent buried bit lines from each other.
The word lines couple the surrounding type gate electrodes 13 of the pillars 11 arranged along the second direction II-II′ with each other. The word lines are extended to intersect with the buried bit lines.
However, according to the typical method shown above, there is a limitation as to reducing a resistance of the buried bit lines because the buried bit lines are formed by implanting dopants into the substrate 10 using the ion implantation process.